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[Software Engineering] xapp341

Description: verilog uart for spartan 3 fpga, its great
Platform: | Size: 21504 | Author: kashif | Hits:

[Com Port] uart

Description: verilog写的与电脑通信的uart，我实验过了，一切都很好，工作很好-verilog written communication and computer uart, I had the experiment, everything is very good, very good work
Platform: | Size: 12288 | Author: 山哥 | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[Com Port] UART

Description: Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
Platform: | Size: 22528 | Author: Roy | Hits:

[VHDL-FPGA-Verilog] uart

Description: this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
Platform: | Size: 4096 | Author: tri | Hits:

[Com Port] UART

Description: 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!
Platform: | Size: 2269184 | Author: Kerwin | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
Platform: | Size: 9216 | Author: dong | Hits:

[VHDL-FPGA-Verilog] uart

Description: verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
Platform: | Size: 3072 | Author: chenzhi | Hits:

[VHDL-FPGA-Verilog] uart-code-Verilog

Description: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Platform: | Size: 10240 | Author: 李明纬 | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Platform: | Size: 15360 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] UART

Description: 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
Platform: | Size: 64512 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
Platform: | Size: 1435648 | Author: 冰色火焰 | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
Platform: | Size: 709632 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog
Platform: | Size: 1024 | Author: xhly | Hits:

[VHDL-FPGA-Verilog] UART

Description: 利用Verilog实现UART收发数据功能-Verilog UART send and receive data functions to achieve
Platform: | Size: 1196032 | Author: 高柯 | Hits:

[VHDL-FPGA-Verilog] my_uart1_VERILOG_using-PLL

Description: Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using PLL
Platform: | Size: 506880 | Author: 林端 | Hits:

[VHDL-FPGA-Verilog] Uart

Description: fpga verilog语言，写的串口通讯，经测试完全没有问题-fpga verilog uart communication
Platform: | Size: 1988608 | Author: 孙祥龙 | Hits:

[VHDL-FPGA-Verilog] verilog--uart

Description: verilog实现uart功能的FPGA应用，适用于Cyclone 2系列-verilog uart function of FPGA applications in the Cyclone Series
Platform: | Size: 88064 | Author: sunlin | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog HDL 入门学习的源代码。 包括双向语法，计数器，状态机，锁存器，uart等-Introduction to learning verilog HDL source code. Including two-way grammar, counters, state machines, latches, uart, etc.
Platform: | Size: 3072 | Author: 鲁东 | Hits:

[VHDL-FPGA-Verilog] Verilog-UART

Description: 功能：UART串口通讯实信实验 描述：本程序共四个模块 模块1：接收数据的波特率发生模块，接收模块在接收到下降沿时，通过标志位启 动该模块的波特率计数器，并在计数中返回一个采样标志位给接受模块， 通知接收模块采样； ---------------------------------------------------------------------- 模块2：数据接收模块，该模块一旦监测到数据输入端有下降沿，就立即启动波 特率（标志位置1），并使能接收标志位rx_int，接收开始； ---------------------------------------------------------------------- 模块3：发送数据的波特率发生模块，发送模块在监测到接收标志位rx_int产生下 降沿时，通过标志位启动该模块的的波特率计数器，并在计数中返回一 个发送标志位给发送模块，通知发送模块发送数据； ---------------------------------------------------------------------- 模块4：数据发送模块，该模块一旦监测到接收标志位rx_int有下降沿，就立即启 动波特率（标志位置1），并使能接收标志位tx_en，发送开始； ---------------------------------------------------------------------- -Verilog UART
Platform: | Size: 16384 | Author: mrmu | Hits:
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